The present invention is directed to the field of non-volatile memory and, more particularly, to I/O based redundancy in a nonvolatile memory array of memory cells capable of storing 2-bits per memory cell.
Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory may be used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. In some applications, the systems and devices may require that the instructions and/or data be retained in some form of permanent/non-volatile storage medium to avoid information loss when the device is turned off or power is removed. Exemplary applications include computer Basic Input Output Systems (BIOS) storage and diskless handheld computing devices such as personal digital assistants.
One type of non-volatile memory that can be used is flash Electrically Erasable Programmable Read Only Memory (xe2x80x9cEEPROMxe2x80x9d) that is commonly referred to as a flash memory. Flash memory is a form of non-volatile storage, which uses a memory cell design with a floating gate. Voltages are applied to the memory cell inputs to program/store charge on the floating gate or to erase/remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate, while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove electronic charge from the floating gate.
One type of memory cells are known as two-bit memory cells due to the ability to store two-bits of data within the memory cell. In two-bit memory devices, a left and right region is used within the memory cell to store two-bits of data. In general, a cell is programmed in the conventional manner using hot electron programming by applying programming voltages to the gate and the left or right region while the other region is grounded.
The memory cell is read in the opposite direction from which it is programmed by similarly applying read voltages to the gate and the left or right region. Each bit can be individually read by using a relatively low gate voltage with polarity that is opposite to the programming voltages. The traditional drain and source of the two-bit memory cells are effectively swapped based on whether the two-bit memory cell is being programmed or erased. Programming and is reading one of the bits leaves the other bit with its information intact and undisturbed.
Flash memory is manufactured to form rows and columns of memory cells that result in a memory array. The memory array is accessed by a row decoder (a wordline decoder) and a column decoder (a bitline decoder). The decoders are used to apply predetermined voltages to a particular memory cell or row of memory cells in the memory array. A sense amplifier is built into the flash memory for sensing the logic value of the selected memory cell(s) when addressed by the row decoder and column decoder. In two-bit memory cells, the decoders control the supply of the programming and reading voltages to the gate and the left and right regions as previously discussed.
In recent years, the density of the memory array on a flash memory has increased dramatically. As the density of the memory array on a flash memory increases, it becomes significantly more difficult to produce perfect flash memory. During fabrication of the flash memory, it is common for the memory array to include one or more defective memory cells due to short circuits, open circuits and other operational defects. In an effort to improve production yields and flash memory reliability, spare or redundant memory cells are typically included on the flash memory. The redundant memory cells provide redundancy of data storage to allow for repair by replacement of the defective memory cells in the memory array.
The flash memory is generally first tested while it is part of a semiconductor wafer joined with other flash memory. If a faulty area containing defective memory cells is located, redundant memory cells are substituted for the defective memory cells in the faulty area. Typically, circuitry is required for selectively deactivating the defective memory cells and activating the redundant memory cells to effect the substitution.
The redundant memory cells and the memory cells in the array are sub-divided into a plurality of redundant blocks with each redundant block further sub-divided into a plurality of sectors. To allow repair of the defective memory cells by the redundant memory cells; an address of a column of defective memory cells is cross-referenced by the flash memory with the location of a column of redundant memory cells. One method of cross-referencing is by assigning an address storage location to the location of the column of redundant memory cells. The address storage location is typically also assigned to a particular redundant block to allow different repairs in different redundant blocks.
Column addresses of defective columns of memory cells that are stored in the particular address storage locations are located within the assigned redundant block location. The defective memory cells are repaired by the columns of redundant memory cells that are assigned to the particular address storage location. The column address of the defective memory cells is stored in the address storage location and later compared against a column address of memory cells that are active within the flash memory during operation. If the addresses match, substitution of the active column of memory cells with a column of redundant memory cells occurs.
A problem arises when the memory cells in a memory array are not addressed sequentially according to their physical location. In this situation, the addresses of the columns of memory cells do not correspond to their physical location within the redundant blocks. Due to the non-sequential configuration, the addressing of columns of memory cells cannot be directly stored to identify the location of the columns of memory cells that are defective. Accordingly, there is a need for systems and methods that are capable of providing redundancy where the order of the memory cells in the memory array are non-sequential.
By way of introduction, this invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells with I/O-based redundancy. More particularly, the present invention relates to I/O-based redundancy for an array of two-bit flash EEPROM cells.
The presently preferred flash memory is capable of I/O based redundancy and includes a core two-bit memory cell array and a redundant two-bit memory cell array. The arrays are subdivided into a plurality of redundant blocks that each contain a plurality of sectors. Each of the sectors are further subdivided into a plurality of I/O blocks.
Within each of the I/O blocks, there are a plurality of two-bit memory cells arranged in columns and rows. The two-bit memory cells are arranged such that a bit identified as a zero bit is at the right edge of the I/O block and the remaining bits are sequentially numbered starting from the left edge of the I/O block. I/O based redundancy is described as xe2x80x9cI/O basedxe2x80x9d since repairs are preformed on specific I/O (or bits) in a specified I/O block within a plurality of corresponding sectors in a specified redundant block. In general, I/O based redundancy allows for repairs within particular I/O blocks by electrically exchanging two-bit memory cells in the core two-bit memory cell array with redundant two-bit memory cells in the redundant two-bit memory cell array.
The flash memory uses addressing to selectively activate the two-bit memory cells and the redundant two-bit memory cells. During testing, when a column of two-bit memory cells in an I/O block is identified as containing a defect, the address of the column of two-bit memory cells is used to repair the defect. In the presently preferred embodiment, a portion of the address is translated by an address translation circuit and stored in a program/read CAM circuit. Translation of the address provides the location of a repair block in the I/O block that includes the column of two-bit memory cells containing the defect. Storage of the translated address provides the location, as well as allowing for subsequent identification of the column of two-bit memory cells containing the defect during operation of the flash memory.
During operation, the address of columns of two-bit memory cells that are currently being accessed by the flash memory to perform read and write operations are translated. The translated addresses are compared to the translated addresses that were stored during testing. A match indicates that the columns of two-bit memory cells that are currently being accessed by the flash memory contain a defect that has been repaired by the I/O based redundancy.
To effect the repair, the translated address is used to identify and disable access by the flash memory to the repair block in the identified I/O block in the core two-bit memory cell array. In addition, a portion of the address of the columns of two-bit memory cells that are currently being accessed by the flash memory are decoded by a redundant Y-decoder circuit. The redundant Y-decoder circuit decodes a portion of the address to selectively configure a plurality of redundant two-bit memory cells. The redundant two-bit memory cells are selectively configured by the redundant Y-decoder circuit to match the configuration of the repair block. Accordingly, the flash memory performs the read or write operation on the redundant two-bit memory cells in place of the repair block in the identified I/O block.
The presently preferred flash memory uses I/O based redundancy to make repairs in I/O blocks where the bits are non-sequentially numbered as previously discussed. These repairs are possible due to the translated addresses that identify the physical location of the repair blocks irrespective of the non-sequential numbering within the I/O blocks. In addition, the repairs are effected by decoding the addresses of the two-bit memory cells to selectively configure the redundant two-bit memory cells in the redundant two-bit memory cell array to match the repair block identified by the translated addresses.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.